In eDram technologies, a ground-to-Vdd level clock signal is translated to a ground-to-Vpp level signal with level translators designed to work between 3-voltage levels. Some eDram technologies, though, need a 4-level Vpp level translator to switch a thin-oxide PFET gate to a safe ‘on-voltage’ from an ‘off-state’ of Vpp.
To improve low voltage operability and timing alignment to Vdd-level clocks, it is desirable to use only thin-oxide, low voltage FETs with a voltage stress limit of Vdd, where Vdd MAX is 1.05V, Vpp is 1.6V and the safe on-voltage is Vpp-Vdd_MAX. In such technologies, the level translator is needed to translate a ground-to-Vdd clock to Vpp2-to-Vpp levels of about 0.55V and 1.60V, respectively.
In a thin-oxide level translator, a static latch powered by Vpp is configured with high-voltage capacitors to receive Vdd level logic signals. In this solution, static, un-gated feedback latches may not switch due to FET manufacturing tolerances in Vt and other devices. Accordingly, un-gated feedback latch designs have been replaced with more predictable gated-feedback latches. Also, in such thin-oxide level translators, capacitors of sufficient size capable of providing reliable switching current need to be large. Large capacitance on the latch nodes, though, limits the operating speed of the static latch. Accordingly, a trade-off between switching robustness and operating speed has to be made.